OneSpin 360™ EC-ASIC Equivalence Checking Solution

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OneSpin's 360™ EC-ASIC Equivalence Checker thoroughly proves, without simulation, that design functionality is maintained through all implementation phases of a design, such as design revisions, synthesis and optimizations, made from RTL to the final netlist – RTL-RTL, RTL-gate and gate-gate – in ASIC/SoC designs. The solution fully automates state and phase mapping via proof-based sequential analysis. A design conditioning component and highly accurate design modeling detect synthesis bugs, synthesis/simulation mismatches and RTL coding bugs that often escape conventional equivalence checking. 360 EC delivers dependable results because it operates completely independently of any synthesis tool, requiring no special synthesis "side files" to handle crucial phases of the equivalence checking flow, such as state mapping, datapath analysis, and ECO verification

Highlights

Exhaustively proves that design functionality is maintained through all implementation steps
Slashes verification time and effort by automated state and phase mapping
Significantly reduces debug time by precise location of bug observability points
Detects more synthesis bugs and synthesis/simulation mismatches than conventional equivalence checkers
Uses an extensive set of fully automatic design consistency checks to rapidly detect common coding errors
Seamlessly integrates with 360 MV to provide a formal verification flow
Leverages decade-long technology development and field use