OneSpin 360™ EC-FPGA Equivalence Checking Solution

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OneSpin's 360™ EC-FPGA solution ensures that advanced FPGA synthesis optimizations – used to achieve competitive functionality, performance, power consumption, and cost targets – do not introduce functional errors. It supports all sequential synthesis optimizations performed in FPGA design flows.

The 360 EC-FPGA solution verifies the optimized design 'as is' without gate-level simulation, design modifications or design restrictions – such as disabling synthesis optimizations. It verifies the whole-chip flat netlists, enabling the most aggressive optimizations leading to highly competitive designs.

The 360 EC-FPGA solution leverages the established 360 EC-ASIC technology with sequential FPGA verification capabilities. It is an automatic, synthesis-tool-independent solution that verifies functional equivalence between the register transfer level (RTL) code and the post-synthesis netlist, as well as between the post-synthesis netlist and the post-place-and-route netlist. It eliminates the need for 'side files' generated by synthesis tools and extensive scripting. A design conditioning component and highly accurate design modeling detect synthesis bugs, synthesis/simulation mismatches and RTL coding bugs that often escape conventional equivalence checking.

Highlights

Ensures that highly optimized, complex FPGA designs are free of synthesis and optimization errors
First equivalence checker to support all sequential FPGA synthesis optimizations
Does not require any simulation or test-vectors
Eliminates the need for synthesis 'side files' and extensive scripting
Enables competitive functionality, performance, power, and cost of FPGA designs
Verifies the FPGA design 'as is' without simulation and design modifications or restrictions
Uses an extensive set of fully automatic design consistency checks to rapidly detect common coding errors
Delivers industry-leading ease of use