OneSpin 360™ EC-FPGA Verification Flow
The 360 EC-FPGA verification flow proceeds in four steps: design consistency checking, automatic state initialization and port mapping, automatic state mapping, and sequential comparison and debug.
- Design Consistency Checking
Solution generates an extensive set of RTL consistency checks (see features) and proves them exhaustively - Automatic State Initialization and Port Mapping
Solution computes a port mapping and state initialization sequences; the initialization sequences reset the two design representations to well-defined initial states as preparation for sequential 'compare' step. - Automatic State Mapping
Functional state mapping is computed and automatically refined by additional mapping points to handle aggressive synthesis optimizations such as retiming or pipelining. - Sequential Comparison and Debug
Automatic, sequential comparison and sequential debugging of the two design
representations till functional equivalence has been reached.
read more about: