Ease of use

The 360 EC-FPGA solution offers industry-leading ease of use. The solution simplifies and accelerates otherwise time-consuming – or even otherwise impossible – verification and debug tasks through:

Automation of design consistency checking, design initialization, state mapping, sequential compare, and sign-off
A fully-featured debug environment to locate the root cause of synthesis and optimization errors (see screenshot below)
A flow-based graphical user interface and Tcl shell
Seamless integration into existing verification flows