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Comprehensive Bug Detection

The 360 EC-ASIC's accurate modeling and sequential analysis detect synthesis bugs, synthesis/simulation mismatches and RTL coding bugs, including the following checks:

• Synthesis full_case
• Synthesis parallel_case
• Bus contention
• Bus floating
• Division by zero
• Negative divisor, exponent or remainder
• Don't care and X assignment
• Read/write, write/write race conditions
• Function without return
• Array boundaries
• Range overflow
• Stuck-at
• Initialization
• Dead code
• User defined

The solution adheres to either simulation or synthesis semantics, and can be configured to obey VHDL's 9-valued and Verilog's 4-valued semantics. It supports advanced, configurable controllability and observability "don't care" handling in RTL-RTL and RTL-gate comparisons.



Screenshot of 360 EC debugger with color coding of diagnosis results in schematic view.


read more about:

• 360 EC-ASIC
• Features
• Fast time to results
• Verification examples