Verification Examples
Integrated Formal Verification Flow
A leading semi-conductor company developed new peripherals and formally verified them using the true functional sign-off methodology of 360 MV. These peripherals have been integrated into 2 ASICs – each of 4 million gates – constituting the central components of a large multiprocessor system. Afterwards, the 360 EC-ASIC solution has been employed to preserve the achieved extreme level of quality through subsequent implementation steps. These ASICs worked right the first time, met an ambitious project schedule, and were critical for the business success of a large wireless communication systems company.Advanced Don't Care Handling
360 EC-ASIC's precise "don't care" handling enabled it to detect a synthesis/simulation mismatch in a commercial microprocessor IP design. The IP vendor removed don't care assignments, essentially changing the entire don't care handling strategy.Comprehensive Bug Detection
The 360 EC-ASIC synthesis/simulation mismatch checks found a synthesis bug for a baseband chip resulting from a "full_case" directive, that is – an incorrect or illegal synthesis tool constraint – which might have necessitated a design respin. Other tools may have given an imprecise warning of a problem, or missed the bug altogether.read more about: