Features

Requires no change to the design team's existing design flow
Significantly eases chip level simulation by ensuring equivalence between implementation levels
Deploys multi-threaded proof engines
Verifies multimillion gate designs
Handles large multipliers and resource sharing with datapath analysis capability
Supports low-power implementations and clock gating
Focuses debug with logic cone extraction and highlighting
Avoids false negatives associated with library cells by qualifying cell libraries with sequential checking
Supports popular design languages: Verilog 95 & 2001; VHDL 87 & 93, and mixed languages
Supports popular computer platforms: Linux 32/64 bit (Opteron/Xeon); Solaris 32/64 bit