Fast time to Results
Automated State Mapping
The 360 EC-ASIC solution achieves fast time to results by using highly automated proof-based sequential analysis to accelerate the mapping of state-holding design elements necessary to capture combinational logic behavior across latch boundaries. This full semantic analysis produces "right first time and all the time" results, eliminating the manual, time-consuming, error-prone iterations generally necessary when using tools that employ name-based mapping routines. The same analysis also automatically and reliably generates the associated phase mapping of sequential elements.Automated Debug
OneSpin 360™ EC-ASIC significantly simplifies and speeds debug, using a proof-based analysis and diagnosis capability that locates bug observability points with pinpoint accuracy. Rapid cross-referencing between the RTL and the gate level netlist then minimizes the back-tracing necessary to locate the bug itself. The 360 EC-ASIC's debug capabilities facilitate a systematic and well-structured debug approach, including value annotation to source code as well as full cross-highlighting between source browser, schematic engine and hierarchy browser, with driver and load tracing.
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