360 MV Features

Provides a verification planning process that maximizes concurrency of verification sub-tasks across a team
Automatically generates an extensive set of design consistency checks to detect common coding errors rapidly
Offers powerful debugging and diagnosis functionality to locate errors
Affords truly interactive check-debug-fix cycles to clean designs from errors
Generates a complete set of monitors that detect unanticipated usage of the IP in the target design during system- level verification
Uses lean verification infrastructure that eases task transfer to remote sites
Requires no changes to the design team's existing design flow
Requires no simulation, no testbenches and no compute farms
Supports popular design languages: Verilog 95 & 2001, VHDL 87 & 93, and mixed languages
Supports popular computer platforms: Linux 32/64 bit (Opteron/Xeon); Solaris 32/64 bit