OneSpin's Datasheets, Articles, White Papers
Product Information
- 360 MV Product Family (please click the link to download datasheet)
The Most Comprehensive Formal Assertion Based Verification Solution - 360 Equivalence Checker – FPGA (please click the link to download datasheet)
The Formal Verification Solution For Advanced Synthesis-Optimized FPGAs - 360 Equivalence Checker – ASIC (please click the link to download datasheet)
The Formal Verification Solution For High Accuracy ASIC Equivalence Checking - Success Story (please click the link to download success story)
360 MV Customer Success
Selection of online publications about 360 MV Product Family
OneSpin offers step-by-step formal verification suite by Richard GoeringOneSpin automates formal assertion/RTL debug by Bill Murray
OneSpin brings formal assertion-based verification (ABV) to the masses by Max Maxfield
OneSpin beschleunigt mit automatischer Fehleranalyse formale Assertion-basierte Verifikation by Gerd Kucera
Further online publications related to 360 MV
Timing Diagrams Ease Formal Property Development by iDESIGNFormal Verification Goes Mainstream by Mike Donlin
Articles about formal verification
Over the last few years, there has been a noticeable uptick in the use of formal verification to augment dynamic verification. Why? A user survey conducted amongst 16 companies that use formal verification.Mixing Formal and Dynamic Verification
Formal methods: Rocket science or mainstream technology? A deeper look published in SCDsource
Formal property checking – what the users say by Richard Goering
Formal property checking – what the vendors say by Richard Goering
Formal verification expands its use model by Bill Murray
Selection of technical articles related to 360 MV
Automated formal method verifies highly-configurable HW/SW interface (SCDsource article)Alcatel-Lucent's Joachim Knaeblein and Hans Sahm describe how they used both automated assertion generation and automated formal methods to verify a complex HW/SW interface in a large SDH/SONET chip – and slashed verification time and effort by 70 percent.
Automated formal method verifies highly-configurable HW/SW interface
Complete Formal Verification of TriCore2 and Other Processors (White Paper)
This paper, first published at DVCon 2007, describes the application of OneSpin's 360 MV to the verification of the TriCore2 processor, Infineon's next generation high-end processor for embedded and safety-critical applications. Unlike other formal approaches, the employed methodology is a self-contained approach to hardware verification, independent of simulation. It systematically eliminates all gaps in the verification plan and in the property set and thus ensures that the IP is free of functional errors – the highest possible quality.
Complete Formal Verification of TriCore2 and Other Processors
Achieving Highest, Certified IP Quality Efficiently (EEtimes article)
The article describes from the perspective of an IP provider the verification of a configurable network processor – called PPv2 – using OneSpin's 360 MV. It explains the details of this verification project and how the following results were achieved:
- error-free functional operation of the PPv2 across all possible configurations
- a verification report that certifies the achieved IP quality and enables rapid IP quality assessment
- a complete description of integration conditions for the IP
- a considerably improved specification
- no IP revision or redesign has been necessary since release
- a total verification effort of 4 engineer-months, about 40% less than that in the simulation-based verification of PPv1
Achieving Completeness in IP Functional Verification (EEtimes article)
360 MV is the only complete functional verification solution. Verification is objectively 'complete' when all output signals of the design under verification have been verified to have their expected values at any point in time for any possible input scenario. This notion of completeness implies 100% input scenario coverage and 100% output behavior coverage, the highest possible coverage that any functional verification can achieve and the key to ensure error-free operation. It can only be achieved when transforming formal verification from the common bug-hunting and corner-case inspection approach into a full 'functional sign-off' approach. The details on complete functional verification compared to other functional verification approaches – be it simulation-based, assertion-based, or formal – is explained in the following EETimes article:
EETimes article: Achieving Completeness in IP Functional Verification