EDSFair seminars by OneSpin Solution about 360 MV
To register for our EDSFair seminars click here (Japanese only)If you cannot attend EDSFair, check out our live webinars about 360 MV
- Formal assertion-based verification for starters – Get Going in a Day
Thursday, 28 January, 11:30 - 12:15, Room DM3.
Assertion-based verification (ABV) is rapidly becoming a mainstream verification approach in companies' RTL verification flows to significantly reduce verification effort and achieve earlier verification closure. This seminar gives a practical introduction to 360 MV and formal ABV applications that ease and speed functional RTL verification with minimal learning effort. By means of real-world design examples you will learn how to use automatically generated assertions for early RTL analysis, how to use assertions to achieve earlier RTL baseline quality, and how to efficiently improve simulation-based coverage using formal ABV.
- Slashing assertion and design debug effort through automated root cause analysis
Thursday, 28 January, 12:30 - 13:15, Room DM3.
The use of assertions sees rapid adoption in the industry. Assertions allow to significantly reduce the effort to verify complex RTL design behavior. Around 40 percent of the total effort for assertion-based verification (ABV) goes into debugging of assertions and designs. In this seminar we give an introduction to formal ABV using 360 MV and demonstrate new powerful root cause analysis techniques that slash assertion and design debug effort. These techniques ease and speed the work of experienced assertion users but also enable non-experts to work efficiently with advanced assertions to increase verification productivity and design confidence. - Advances in formal assertion-based verification that ease and speed exhaustive operation- and transaction-level verification
Friday, 29 January, 10:30 - 11:15, Room DM3.
Assertion-based verification (ABV) is one of the major industry trends to increase verification productivity and quality for RTL designs. This seminar demonstrates recent advances in formal ABV using 360 MV. We present the first closed-loop formal ABV process that feature automatic formal coverage analysis. The process enables the efficient, gap-free verification of high-level design operations and transactions using SystemVerilog assertions (SVA). A simple SVA-modeling layer is shown that enables users to develop the required high-level assertions directly from timing diagrams, easing assertion development, debugging and maintenance. All concepts are illustrated by real-life verification examples.
Thanyapat Sakunkonchak
Field Application Engineer, OneSpin Solutions Japan KK
thanyapat.sakunkonchak@onespin-solutions.com