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OneSpin Verification Solutions Overview

OneSpin offers customer-proven, award-winning formal verification solutions for functional verification and equivalence checking in ASIC and FPGA flows. They can be used either stand-alone or integrated, providing a unique, seamless formal verification flow. This flow assures highest quality at specification, RT and gate levels and boosts verification productivity. The solutions – based on a common technology foundation – have been field-proven on hundreds of customer designs.

360 MV Solutions 360 EC Solutions Solutions The OneSpin 360™ Module Verifier is EDA's first and only functional verification solution to efficiently achieve error-free functional operation for a broad range of peripherals, processors and sub-systems of up to a few hundred thousand lines of RTL-code. It provides a unique, automatic completeness analysis that detects all verification gaps and predictably guides engineers from verification planning to final, documented true functional sign-off.

The OneSpin 360™ Equivalence Checker is a highly automated verification solution to show the functional equivalence of design representations. It can be used stand-alone to assure full-chip implementation design equivalence in both ASIC and FPGA flows or in conjunction with the 360 Module Verifier to preserve highest design quality through subsequent implementation and optimization phases.

The OneSpin 360 Integrated Verification Flow

The OneSpin 360 flow enables designers and verification engineers to achieve and preserve the highest design quality – at multiple levels of abstraction – that is essential to the design, integration and re-use of error-free intellectual property (IP), both proprietary and third party. The integration of 360 MV and 360 EC leverages the capabilities of the individual solutions and provides additional synergy effects:
  • Deploys a joint methodology to achieve and preserve True Functional Sign-off
  • Employs a common user interface that reduces adoption time and effort
  • Utilizes a shared verification infrastructure that enables direct re-use of results throughout the flow
  • Eliminates the interfacing problems often experienced when integrating stand-alone tools
  • Offers sophisticated sequential debug and diagnosis capabilities

True Functional Sign-Off

The OneSpin 360™ verification flow deploys a single, accurate formal design modeling methodology – shared by 360 MV and 360 EC – to ensure dependable and consistent functional verification results in ASIC and FPGA flows. The 360 MV solution enables error-free functional operation at RT level, leading to a true functional sign-off. The 360 EC solution assures that 360 MV's true functional sign off quality is maintained through subsequent ASIC or FPGA implementation steps.

Faster Time To Results

The OneSpin 360™ flow's Tcl-shell and GUI improves verification productivity through efficient results sharing and re-use without the necessity for additional tool interfacing, re-compilation and re-proof. It speeds 360 EC's debug of non-equivalent design representations through sophisticated sequential diagnosis capabilities using 360 MV. Furthermore, 360 MV checks internal signal and state constraints that are used to focus 360 EC's analysis on real world behavior, thus excluding unrealizable scenarios that cause time wasting false negatives during equivalence checking. Such constraint proofs by 360 MV can be executed on demand, or derived as a by-product of a complete module verification. The latter also identifies and validates environmental constraints for use by 360 EC.

Advanced Design Conditioning

The integrated flow is complemented by an optional design conditioning phase that performs a wide range of functional design consistency checks. These checks avoid design iterations by identifying and enabling the correction of RTL coding errors and synthesis/simulation mismatches early in the flow, and provide analysis data for use in subsequent design and verification phases.