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Product and Methodology Training

OneSpin offers professional product and methodology trainings, each combining lectures and hands-on labs.

360 MV Introductory Course

Goal: Make the participants familiar with 360 MV and enable them to participate in a verification project using 360 MV
Duration: 2 days
Prerequisites: HDL design knowledge
Content: Introduction to formal verification, introduction to 360 MV's methodology, design compilation, automated consistency checks and their debugging, the property language, writing operation properties, the debugging and diagnosis environment for properties and RTL code, design exploration and verification using 360 MV

Goal: Make the participants familiar with the concepts, methodology and tooling for complete formal verification and enable them to conduct a complete formal verification on smaller modules to ensure error-free behavior
Duration: 2 days
Prerequisites: 360 MV Introductory Course
Content: Introduction to complete formal verification, the FormalDoublePASS– completeness methodology, verification planning, writing complete property sets, automatic completeness analysis and debugging to systematically detect and close all verification gaps, reaching the termination criterion: certified 100% input scenario coverage and 100% output behaviour coverage; final, documented 'True Functional Sign-Off'

Goal: Make the participants familiar with 360 EC-ASIC and enable them to show the functional equivalence of two design representations in ASIC flows
Duration: 2 days
Prerequisites: HDL design and ASIC synthesis knowledge
Content: design compilation, automated consistency checks and their debugging, application of automated state and port mapping, the compare task, handling of the debugging and diagnosis environment to locate and correct functional differences to achieve implementation sign-off

Goal: Make the participants familiar with 360 EC-FPGA and enable them to show the functional equivalence of two design representations in FPGA flows
Duration: 2 days
Prerequisites: HDL design and FPGA synthesis knowledge
Content: design compilation, automated consistency checks and their debugging, computation of initial states for sequential comparison, the compare task, handling of the debugging environment to locate and correct functional differences to achieve implementation sign-off

Location: all courses are offered at OneSpin's offices. Courses at the customers premises' can also be arranged world-wide
Maximum number of participants: 10
For pricing and further information, please email to info@onespin-solutions.com