New Series of Assertion-Based Verification Webinars
Don’t miss our new “Verification Beyond Doubt” webinars. Meet our verification experts who explain and demonstrate best-practices in assertion-based verification (ABV) which will save you verification effort and significantly increase your confidence in verification results – no matter if you are new to formal verification or an experienced user.These webinars are the continuation of our series
of formal ABV webinars that have been attended by hundreds of engineers and managers in the past 6 months.
Here’s some of their feedback:
• “Clearly beyond the capabilities
of our current verification approach”
• “As an experienced formal
verification user, I especially liked your operational ABV methodology.”
• “The
embedded example for automatic detection of verification holes
was really nice.”
• “Excellent webinar, easy to follow;
interesting tool.”
Webinar 1: "Operational ABV + Formal Coverage Analysis = 100% Coverage”
This webinar explains how OneSpin’s 360 MV can eliminate the need for writing block-level test benches while efficiently achieving certified 100% design coverage. See how 360 MV‘s Operational ABV methodology and formal coverage analysis simplifies verification planning, guides high-coverage assertion development and automatically identifies any verification holes, i.e. yet unverified design functionality – proven in more than 300 verification projects.| Date: Tuesday, 28 September, 2010 Time: 11 a.m. PDT (8:00 p.m. CEST) If you would like to attend this webinar, please register here |
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| Date: Thursday, 30 September 2010, Time: 11 a.m. CEST (6:00 p.m. JST) If you would like to attend this webinar, please register here |
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Webinar 2: "Preventing X-related Bugs through 4-state-logic Formal Analysis"
This webinar explains OneSpin’s 360 MV 4-state-logic formal analysis that enables exhaustive pre-synthesis analysis of X-propagation while considering X-optimism and X-pessimism simultaneously. See how this analysis also avoids RTL-netlist mismatches at the RTL level and thus effectively eliminates the need to run gate-level simulations to check for dangerous x-propagation. It detects, e.g., unintended X-propagation caused by uninitialized registers and ensures safe use of X’s for RTL verification and synthesis optimization."| Date: Thursday, 30 September, 2010 Time: 11 a.m. PDT (8:00 p.m. CEST) If you would like to attend this webinar, please register here |
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| Date: Tuesday, 28 September, 2010, Time: 11 a.m. CEST (6:00 p.m. JST) If you would like to attend this webinar, please register here |
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For more information about 360 MV's new X-Checking capabilities see our press release.
New: Recorded Webinars
If you have missed our last series of Assertion-Based Verification Webinars'Get Going in a Day' and 'Get Ahead – Advances in in SVA-based formal ABV'
we now offer you the possibility to request a recording of these webinars for online viewing.
'Get Going in a Day'
This introductory webinar explains formal ABV applications that ease and speed functional RTL verification with minimal
learning effort. The webinar uses real design examples and 360 MV to show:
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'Get Ahead – Advances in SVA-based formal ABV'
This webinar shows recent advances in SVA-based formal ABV that ease and speed exhaustive operation-
and transaction-level verification. The webinar uses real design examples and 360 MV to show:
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Datasheets, Whitepapers and Articles
Product Information
360 MV Product Family (please click the link to download datasheet)The Most Comprehensive Formal Assertion Based Verification Solution
Whitepaper
Alcatel-Lucent's J. Knaeblein and H. Sahm describe how they used automated assertion generation and OneSpin's 360 MV to verify a complex HW/SW interface in a large SDH/SONET chip – and slashed verification time and effort by 70 percent.Automated formal method verifies highly-configurable HW/SW interface
Articles and Viewpoints
OneSpin advances formal assertion/RTL debug automation by Bill MurrayOneSpin offers step-by-step formal verification suite by Richard Goering
Formal methods: Rocket science or mainstream technology? A deeper look published in SCDsource
Timing Diagrams Ease Formal Property Development published in iDESIGN