Revolutionizing Mission
Critical Verification

From ChipDesign: The EDA Industry Macro Projections for 2016

Raik Brinkmann, president and chief executive officer at OneSpin Solutions wrote:

“OneSpin Solutions has witnessed the push toward automotive safety for more than two years. Demand will further increase as designers learn how to apply the ISO26262 standard. I’m not sure that security will come to the forefront in 2016 because there no standards as yet and ad hoc approaches will dominate. However, the pressure for security standards will be high, just as ISO26262 was for automotive.

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From Chip Design: Technology Implications for 2016

 

Raik Brinkmann, president and CEO of OneSpin Solutions, noted:
”High-level synthesis will get more traction because the demand is there. As more designs get comfortable using the SystemC/C++ level, demand for EDA tools supporting the task will increase, including formal verification.  Additionally, algorithmic design will be driven further in 2016 by applications on FPGAs to reduce power and increase performance over GPU. That suggests FPGA implementation and verification flows will require more automation to improve turnaround time, a viable opportunity for EDA vendors.  Finally, verification challenges on the hardware/firmware interface will increase as more complex blocks are generated and need firmware to access and drive their functions.

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From Semiconductor Engineering: Tools and Flows in 2015

Another area that has seen growing acceptance in the past few years is Formal Verification. “Formal continues to be deployed in situations where preset applications work well,” says Kelf. “More advanced applications such as system security analysis and system-level verification testing will emerge.”

Kelf also predicts that the most important development for formal in 2015 will be “a proliferation of the technology to designers where it may be used to speed up the early checking of design code before it is submitted into the verification regression environment.”

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From DeepChip: Xilinx OneSpin EC Endorsement

"Hey, John,
You mention that Calypto has the only sequential EC tool around. Well, OneSpin has a powerful Sequential EC tool, OneSpin 360 EC, that 
we at Xilinx use extensively. It is a technology that should not be ignored!" "You might want to look at OneSpin in Munich as an alternative to Calypto LEC."

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From Tech Design Forum: Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match. 

The growth in the use of C++ and SystemC for describing electronic hardware components, particularly at the algorithmic level, has been one of the best-kept secrets in EDA. Although multiple SystemC applications are envisaged –– for example, abstract hardware, virtual platforms and configurable intellectual property (IP) –– the use of SystemC for modeling algorithms and then using them as the input to High Level Synthesis (HLS) tools is becoming much more common.

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From Semiconductor Engineering: Can Cars Be Hack-Proof?

Dave Kelf, vice president of marketing at OneSpin Solutions, has seen this firsthand with automotive companies. “In terms of verification, they have to do what everyone else is doing—but much better. Everyone else can say they can get away with 90% to 95% coverage of the design. These guys have to do 100%, no mucking about. That means that it’s the usual story around verification, but it’s more rigorous.”

Verifying how a chip in the field will operate under varying design conditions with a number of potential faults is a difficult verification problem, he stressed. To this end, OneSpin has been working with other tool providers to determine the best way to build a tool that allows for fault insertion into the design — which cannot be changed — whereby the fault must be inserted on top of the design as it stands, and to see the effect of that on the rest of the design as the fault propagates. “That is a huge EDA problem. So as you find all these unusual design issues you find opportunities for EDA to help figure out solutions for those—on top of the verification guys within the companies are already doing. Security is another one of those.”

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From Elektroniknet.de: Apps für die formale Verifikation

Formale Verifikationstechnologie punktgenau auf bestimmte Anwendungen und Probleme zu fokussieren, das ermöglicht die formale Plattform 360 – DV Launchpad von One Spin - eine Chance für Drittanbieter.

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From Semiconductor Engineering: EDA’s Clouded Future

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast.

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From EDA Cafe, The Breker Treker: Rain or Shine for the EDA Cloud?

Recent announcements from IBM and others about supporting EDA tools in the cloud have spurred renewed discussion on this topic, including here at The Breker Trekker. As expected, the recent posts have been very popular with our readers. Those of you who have been following this topic for a while may recall that, almost exactly two years ago, EDA vendor OneSpin announced cloud support for their formal tools. We invited their VP of Marketing, Dave Kelf, to fill us in their experiences since then:

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